1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more particularly, to an integrated circuit device comprising a plurality of functional modules each having a test circuit.
2. Description of the Background Art
In a conventional integrated circuit device, one functional module such as a random access memory (RAM), a read only memory (ROM), an arithmetic logic unit (ALU) or a programmable logic array (PLA) is generally implemented on a single chip, and this allows test data to be inputted/outputted into/from the module directly from the outside of the chip. As a result, a function test is easily performed.
However, as integrated circuits are made larger in scale in recent years, a so-called structured design method for building block has been employed in many cases, as a manner of designing a large scaled integrated circuit, which allows chip as a whole to have desired functions, by designing individual functional modules each having its own subfunction and then arranging a combination of a plurality of the functional modules thus designed on the chip. In the integrated circuit device having a plurality of functional modules arranged on a single chip, it is effective to perform a function test for a subfunction of each functional module as a design unit. Although for testing subfunction of each functional module, there is a method of forming a scan path having all shift register latches (SRL) connected in series each provided at an input/output node as a test point of each module to serially and externally input and output test data in/from the scan path, the method requires a scan path to be longer when the number of modules is large, making it difficult to test the functional modules quickly. As a solution of this problem, the scan path may be divided, one for each functional module, so that test data is directly and externally inputted/outputted to/from only the functional module to be tested.
FIG. 9 is diagram showing an example of the conventional integrated circuit comprised of a plurality of functional modules each including a test circuit for testing subfunction of each module as described above. First, a structure of the conventional integrated circuit will be described with reference to FIG. 9. In FIG. 9, an integrated circuit (chip) 1 comprises a plurality of functional modules 2a, 2b, . . . . In order to test the functional modules independently, a test circuit is provided for each functional module. Described in more detail, the functional module 2a comprises a test circuit including a scan path comprised of series-connected SRLs 3a, 3b, 3c and 3d, a tri-state buffer 4a connected to an output portion of the scan path and for controlling an output of the scan path, and a selection circuit 50a comprising an address decoder for controlling the tri-state buffer 4a, and a circuit 60a which subfunction is to be tested by the test circuit. Similarly, the functional module 2b comprises a test circuit including a scan path comprised of series-connected SRLs 3e, 3f, 3g and 3h, a tri-state buffer 4b connected to an output portion of the scan path and for controlling an output of the scan path, and a selection circuit 50b comprising an address decoder for controlling the tri-state buffer 4b, and a circuit 60b which subfunction is to be tested by the test circuit.
The above described scan path provided for each functional module has one end connected to a common input data signal line 7 and the other end connected to a common output data signal line 6. Test data SDI to be supplied to each functional module is inputted from the outside of the chip to the common input data signal line 7 through a test data input terminal 11 and a test data output from each functional module is outputted as a test data output SDO to the outside of the chip through the common output data signal line 6 and a test data output terminal 10.
In each functional module, a scan path enable terminal SPE of the selection circuit 50 comprising the address decoder is connected to an output control signal line of the tri-state buffer 4, so that when the selection circuit 50 is selected by an address signal which will be described later, an output of the corresponding tri-state buffer 4 enters an enable state.
An address signal line 48 is connected to each selection circuit 50 comprising an address decoder, so that an address signal inputted from the outside of the chip through an address signal input terminal 49 selects a selection circuit 50 of any of the test circuits.
On the other hand, scan path control signals for the scan paths such as shift clocks and strobe signals are inputted from the outside of the chip through a control signal input terminal 13 and supplied to each scan path through a common control signal line 9 and each selection circuit 50.
FIG. 10 is a block diagram showing in detail transmission of signals between a test circuit and a circuit to be tested in the respective module of an integrated circuit shown in FIG. 9.
Now an operation of the conventional integrated circuit shown in FIGS. 9 and 10 will be described.
In the normal mode operation, referring to FIG. 10, data to be processed passes through the SRLs 3a and 3b without being latched and is applied to the circuit 60a of the functional module 2a. Thereafter, the data processed by the circuit 60a passes through the SRLs 3c and 3d without being latched and is applied to the functional module 2b. The applied data further passes through the SRLs 3e and 3f without being latched and is applied to the circuit 60b. Thereafter, the data further processed by the circuit 60b passes through the SRLs 3g and 3h without being latched and is outputted from the functional module 2b.
In the integrated circuit shown in FIGS. 9 and 10, each functional module 2 is tested as follows. Namely, in each functional module 2, test data is serially inputted to the scan path comprised of SRLs 3 through the test data input terminal 11 and the common input signal line 7. Then, a function of each circuit 60 is tested by the test data inputted to each scan path, so that the test data output from the circuit 60 is latched in the SRL of the scan path.
More specifically, test data latched by the SRLs at the input side of each module is applied to the circuit 60 to be tested. Then, test data output from the circuit 60 is captured by the SRLs at the output side of each module. Broken lines indicate control signals for driving SRLs in FIG. 10. Thereafter, the data output is serially outputted through the common output data signal line 6 and the test data output terminal 10 to the outside of the chip. The result of such test is determined by the external determination circuit (not shown).
Since an output of each scan path is connected to the common output data signal line 6 in the above described structure, there is possibility of contention of the outputs from the scan paths on the common output data signal line 6, that is, data collision. Accordingly, in a function test, only a single scan path has to be in the enable state at all times.
Thus, any one of the scan paths is to be selected by an address signal applied from the outside of the chip through the address signal input terminal 49. Therefore, for example, in order to render only the scan path comprised of the SRLs 3a, 3b, 3c and 3d in the functional module 2a to enter the enable state, an address signal corresponding to the selection circuit 50a is inputted to the address signal line 48 through the address signal input terminal 49 to select the selection circuit 50a which is the address decoder. As a result, the tri-state buffer 4a is driven by the selection circuit 50a to enter an output enable state. An integrated circuit device is disclosed, for example, in U.S. Pat. No. 4,701,921, in which a test circuit comprising a scan path and a selection circuit is modularized and furthermore, an address decoder is employed as a selection circuit as described above.
FIG. 11 is a block diagram showing another example of a conventional integrated circuit comprising a plurality of functional modules.
The integrated circuit of FIG. 11 is for achieving an additional function by arranging on a chip a combination of a hierarchical functional module 36 comprising a plurality of functional modules 2c, 2d and 2e, and individual functional modules 2a and 2b. More specifically, the term "hierarchical" means a structure made by arranging a chip having a one chip layout including some modules (2c, 2d and 2e) on a new chip 1 together with some individual modules (2a and 2b).
It is assumed that each functional module comprises a test circuit including a scan path and a selection circuit, similar to the example of FIG. 9. An address signal for the hierarchical functional module 36 is inputted through an address input terminal 51 and transmitted on an address signal line 50. Address signals for the individual functional modules 2a and 2b are inputted through an address signal input terminal 49 and transmitted on an address signal line 48.
A physical layout of the hierarchical functional module 36 is determined with signal lines for a function test of each module being interconnected, and the design pattern is standardized and registered as content unchangeable (i.e., incorporated into a library of functional modules available to circuit designer). Accordingly, in such a hierarchical functional module 36, for example, the number of bits of an address signal line or the like is fixed and registered and the contents thereof can not be changed. The conventional integrated circuit device comprising such a hierarchical test circuit is disclosed in Japanese Patent Laying-Open No. 62-93672.
In the above described conventional integrated circuit, a structure of a selection circuit as an address decoder and the number of bits of an address line are determined in accordance with a circuit structure such as the number of functional modules or the like on a chip. However, in a functional module which is made into a library, the structure of the selection circuit as the address decoder and the number of bits of the address signal line are fixed and registered, and can not be changed.
Accordingly, in interconnecting signal lines for a function test of the entire integrated circuit, the output data signal line 6, the input data signal line 7 and the control signal line 9 of FIG. 11 can be used in common by the hierarchical functional modules 36 which is made into a library, and the functional modules 2a and 2b each being made into a library individually. However, it is often difficult for an address signal line for selecting a scan path of each functional module to be used in common because as shown in FIG. 11, the hierarchical functional module 36 and the individual functional modules 2a and 2b often differ in the number of bits of the address signals for selecting the scan paths.
In addition, in the functional modules 36 made into a library, each address decoder as a selection circuit in each of the modules 2c-2e is configured to the same structure. Accordingly, in case there exist on a single integrated circuit a plurality of functional modules which are made into libraries with test circuits included, the plurality of functional modules are to have the same selection circuits, so that it is highly possible that the plurality of functional modules are selected simultaneously to cause the contention of the outputs of the scan paths on an output data signal line. Therefore, it is required that the address signal line be provided separately for each module.
As the foregoing, it is not appropriate to make into a library the conventional integrated circuit having a scan path selecting means comprising an address decoder, because of the increased number of signal lines.